As a method for isolating elements of a semiconductor device, a great deal of attention is being directed towards a shallow trench isolation (STI) process where a silicon nitride layer is formed on a silicon substrate, shallow trenches are formed via etching or photolithography, and a dielectric layer is deposited to fill the trenches. Due to variation in the depth of trenches, or lines, formed in this manner, it is typically necessary to deposit an excess of dielectric material on top of the substrate to ensure complete filling of all trenches.
The excess dielectric material (e.g., an oxide) is then typically removed by a chemical-mechanical planarization process to expose the silicon nitride layer. When the silicon nitride layer is exposed, the largest area of the substrate exposed to the chemical-mechanical polishing system comprises silicon nitride, which must then be polished to achieve a highly planar and uniform surface. Generally, past practice has been to emphasize selectivity for oxide polishing in preference to silicon nitride polishing. Thus, the silicon nitride layer has served as a stopping layer during the chemical-mechanical planarization process, as the overall polishing rate has decreased upon exposure of the silicon nitride layer. Oxide line widths are becoming smaller as etching technology progresses. As oxide lines widths decrease, it is often desirable to utilize polishing systems having selectivity for silicon nitride over oxide polishing, which can minimize defectivity in the oxide lines formed on the substrate surface.
Compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries) typically contain an abrasive material in a liquid carrier and are applied to a surface by contacting the surface with a polishing pad saturated with the polishing composition. Typical abrasive materials include silicon dioxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide. U.S. Pat. No. 5,527,423, for example, describes a method for chemically-mechanically polishing a metal layer by contacting the surface with a polishing slurry comprising high purity fine metal oxide particles in an aqueous medium. Polishing compositions are typically used in conjunction with polishing pads (e.g., a polishing cloth or disk). Suitable polishing pads are described in U.S. Pat. Nos. 6,062,968, 6,117,000, and 6,126,532, which disclose the use of sintered polyurethane polishing pads having an open-celled porous network, and U.S. Pat. No. 5,489,233, which discloses the use of solid polishing pads having a surface texture or pattern. Instead of or in addition to being suspended in the polishing composition, the abrasive material may be incorporated into the polishing pad. U.S. Pat. No. 5,958,794 discloses a fixed abrasive polishing pad.
Several chemical-mechanical polishing (CMP) compositions for polishing substrates containing low dielectric constant materials (e.g., oxide) are known. For example, U.S. Pat. No. 6,043,155 discloses a cerium oxide-based slurry for inorganic and organic insulating films, having selectivity for silicon dioxide versus silicon nitride polishing. U.S. Patent Application Publication 2002/0168857 A1 discloses a method for manufacturing a semiconductor device in which silicon dioxide is deposited on a silicon nitride film patterned with trenches, and a two-stage chemical-mechanical polishing process is then performed to selectively remove overlying silicon dioxide, thus leaving trenches filled with silicon dioxide. Thus, there remains a need in the art for polishing compositions and methods having the reverse selectivity, for selectively removing silicon nitride over underlying dielectric components.
The invention provides such a composition and method. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.